Research Topics


Overview

各式之通訊與傳輸技術已經逐漸融入現代人的生活與家庭之中,提供人們無拘無束之通訊及資訊之傳遞與接收。一般而言,透過有線的通訊服務,如同軸電纜(cable modem)及高速序列傳輸器可大量快速的傳遞資訊,而無線之通信如及無線網路(802.11n, 802.16e/m與802.11ac/ad)等可隨時地有效的收發資訊與視訊。通訊科技之進步相信是帶動國內高科技產業之主要動力之一。生醫電子則為另一個未來之跨領域研究可突破之領域。過去數年,本人亦從事智慧型助聽器之研究,尤以單音節(如中文)為主。

通訊系統所需之積體電路是決定各項通訊產品性能及市場競爭力的一項關鍵因素。然而,通訊用積體電路之設計需結合積體電路設計,通訊及信號處理等領域的知識,其本身極具研究之挑戰性。故近年研究重點之一在寬頻通訊之線路及架構設計。因應助聽器及生醫電子之應用,低電壓(近或低於threshold voltage) 及極低功率之關鍵模組如內嵌式SRAM及時序產生器等亦為研究主題。而因應個人通訊之渴望,整合之接收機晶片及強調低功率之IC產品更是一股未之能禦之風潮。本人除了和業界進行相關研究計畫外,和交大電子、電信與資工之教授合作使用 60GHz 之室內十億級位元傳輸率之無線基頻傳收機(802.15.3c, 802.11 ac/ad)在傳輸能力上可以達成10Gpbs以上的速度。此外並在Serial link於off-chip及on-chip之高速傳輸(5Gbps~40Gbps)及LV/LP embedded memory經濟部學界科專(2009~2012)和交大、中央老師合作及業界如智原、台積電、凌陽、創意、鑫創、世芯和工研院電通所等合作,在高速混合信號電路設計及傳收器架構上及LV/LP電路上持續研究,近五年(2009~2013)共發展16篇國際期刊論文,33篇國際會議論文並獲得2項專利(申請中11項)建教合作技術移轉與專利授權7項


On-going Projects

[1] 總計畫主持人,5Gb/s 等級之第五代行動通訊無線基頻傳收機及其關鍵信號處理模組 (Beyond 5Gb/s, 5th generation mobile communication transceiver and key signal processing modules), National Science Council, May 2014 - April 2016 (兩年計劃)

[2] 主持人,影像輔助語音處理 (Video-Assisted Speech Processing), National Science Council, August 2014 - July 2017 (三年計劃)

[3] Event-Driven Energy-Efficient Sensing Platform for Wearable Application


Wireless Communication Research Group

適用於60 GHz室內無線基頻傳收機之硬體架構及晶片實現

Design and Implementation of Baseband Receiver Architecture for 60 GHz Indoor Wireless Transmission


Digital Hearing-aids Research Group

華語數位助聽器之彈性音高語音偵測和噪音消除設計與實現

Pitch Based Voice Activity Detection and Noise Reduction for Mandarin Hearing Aid System


Serial Link Research Group

高速傳輸連接傳收器積體電路設計

40 Gbps All Digital Concurrent Adaptive Decision Feedback Equalizer for 2-PAM Systems

 


Memory Research Group

低電壓低功率時脈與高可靠度記憶體設計

LV/LP Clocking and High Reliability Memory Design


Research Achievement

I.   高速傳輸連接傳收器積體電路設計:6-10Gbps、高速序列傳送器及6Gbps高速    序列資料回復電路及其模組產生器。(如圖一)。

 

[1]  W. C. Liu, C. H. Lin, S. J. Jou, H. W Lu, C. C. Su, K. W. Hong, K. H. Cheng , S. W. Yang, M. H Sheu, “A Micro-Network on Chip with 10-Gb/s Transmission Link,” IEEE    Asian Solid-State Circuit Conference, Nov. 2009.

[2]  Y. C. Lin, M. T. Shiue and S. J. Jou, “10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop,” IEEE Inter. Symp. Circuits and Systems, May 2009, pp.1839-1912. (EI)

[3]  C. S. Lin, Y. C. Lin, S. J. Jou+ and M. T. Shiou, “Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System,” IEEE Custom Integrated Circuits Conference, Sept. 2007.

[4]  C. M. Chu, C. H. Lin and S. J. Jou, “6Gbps Serial Transmitter with Pre-Emphasis,”IEEE International Symp. on VLSI Design, Automation and Test, April 2007, pp.73-76.

[5]  H. Y. Chen and S. J. Jou, “Novel Programmable FIR Filter Based on Higher Radix Recoding  for Low-power and High-performance Applications,” IEEE Int. Conf. Acoustics, Speech, and Signal Processing, April 2007, pp. III-1473–1476.

[6]  S. J. Jou, C. H. Lin, Y. H. Chen and Z. H. Li, “Design and Analysis of Digital Data Recovery Circuits Using Oversampling Technique,” IET Proc. Circuits, Devices and     Systems, Vol.1, No.1, Feb. 2007, pp.93-102.(SCI, EI).

[7]  M. C. Lin, H. Y. Chen and S. J. Jou, “Design Techniques for High-Speed Multirate   Multistage FIR Digital Filters,” International Journal of Electronics, Oct. 2006, pp.699-721.  (SCI, EI)

[8]  H. Y. Chen, C. H. Lin and S. J. Jou, “DC-Balanced Low-jitter Transmission Code for 4-PAM Signaling,” IEEE Trans. Circuits and Systems, part II, Vol.53, No.9, Sept. 2006, pp.827-831.  (SCI, EI).

[9]  C. H. Lin, C. N. Chen, Y. J. Wang, J. Y. Hsiao and and S. J. Jou, “Parallel Scrambler for High-Speed Applications,” IEEE Trans. Circuits and Systems, part II, Vol. 53, No.7, July 2006, pp.558-562 .  (SCI, EI).

[10] J. H. Huang, C. H. Lin and S. J. Jou, “Adaptive Quadrature Clock Generator,”  IEEE International Symp. on VLSI Design, Automation and Test, April 2006, pp.203-206.

[11] C. H. Lin, C. H., C. N. Chen and S. J. Jou, “Multi-Gigabit Pre-emphasis Design and  Analysis  for Serial Link,” IEICE Trans. on Electronics, Vol.E88-C, No.10, Oct. 2005, pp.2009-2019. (SCI, EI).

 

圖一(b) Digital ADF Equalizer for 10GBase-LX4 Ethernet System

II.  無線寬頻通訊OFDM之接收器-架構與線路如基頻載波,脈波(clock),   時序(Timing)回復器及通道估測與適應性等化器等之積體電路(如圖二)。

 

[1]  H. Y. Chen, M. L. Ku, S. J. Jou and C. C. Huang, “A Robust Channel Estimator for        High-Mobility,” To be published, IEEE Trans. Circuits and Systems, part I April, 2010.      (SCI, EI).

[2]  C. H. Liu, C. C. Lin, S. W. Yen, C. L Chen, H. C. Chang, C.Y. Lee, Y.S. Hsu and S. J. Jou, “Design of a Multimode QC-LDPC Decoder based on Shift-Routing Network (SRN),” IEEE Trans. Circuits and Systems, part II, Sept. 2009.  (SCI, EI)

[3]  S. W. Yen, M. C. Hu, C. L. Chen, H. C. Chang, S. J. Jou, and C. Y. Lee, “A 0.92mm2 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application,” IEEE Custom Integrated Circuits Conference, Sept. 2009, pp191-194.

[4]  H. S. Hu, H. Y. Chen and S. J. Jou, “A Novel FFT Architecture for DFT-based Channel Estimation in IEEE 802.16e,” IEEE International Symp. on VLSI Design, Automation and  Test, April 2009, pp.150-153. (EI).

[5]  T. C. Wei, W. C. Liu, C. Y. Tseng and S. J. Jou, “ Synchronization Design of an OFDM Receiver for DVB-T/H Application,” IEEE Transactions on Consumer Electronics,             May 2009, pp.336-341. (SCI, EI).

[6]  T. C. Wei, W. C. Liu, and S. J. Jou, “A Jointed Mode Detection and Symbol Detection Scheme for DVB-T,” IEEE Transactions on Consumer Electronics, Vol.54, No.2,              May 2008, pp.336-341. (SCI, EI).

[7]  C. H. Liu, S. W. Yen, C. L. Chen, H. C. Chang, C. Y. Lee, Y. S. Hsu and S. J. Jou, “An LDPC Decoder Chip Based on Self-Routing Network for 802.16e Applications,” IEEE  Journal of Solid-State Circuits, Vol.43, No.3, March 2008, pp.684-694. (SCI, EI)

[8]  T. C. Wei, W. C. Liu, C. Y. Tseng, S. S. Long, S. J. Jou, and M. T. Shiue, “A 28mW  OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization,” IEEE  Custom Integrated Circuits Conference, Sept. 2008, pp.351-354.

[9]  J. N. Lin, H. Y. Chen, T. C. Wei and S. J. Jou, “Symbol and Carrier Frequency Offset Synchronization for IEEE802.16e,” IEEE Inter. Symp. Circuits and Systems, May 2008,      pp. 3082 - 3085.

[10] C.Y. Tseng, T.C. Wei, W.C.  Liu and S. J. Jou, “Low Power and Power Aware Design      for DVB-T/H Baseband Inner Receiver,” IEEE International Symp. on VLSI Design, Automation and Test, April 2007, pp.204-207.

[11] W. C. Liu, T. C. Wei and S. J. Jou, “Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H,” IEEE Inter. Symp. Circuits and Systems, May 2007,  pp.2092-2095.

[12] W.C.  Liu, T.C. Wei and S. J. Jou, “Two-Stage Scattered Pilot Synchronization with   Channel Estimation ScatteredPilots Pre-Filling for DVB-T/H,” IEEE International Symp.         on VLSI Design, Automation and Test, April 2007, pp.200-203.

[13] T. Z. Wei, S. J. Jou and M. T. Shieu, “Memory Reduction ICFO Estimation Architecture    for DVB-T,” IEEE Inter. Symp. Circuits and Systems, May 2006, pp.3406-3409.

 

圖二 Die photo of LDPC decoder and DVB-T/H Baseband Receiver

 

 

 III. Low power and noise aware Logic, SRAM and data path design for Nano CMOS

 

[1]  J. Y. Lin, M. H. Tu, M. C. Tsai, S. J. Jou and C. T. Chuang, “Asymmetrical Write-Assist     for Single-End SRAM Operation,” IEEE International SOC Conference, Sept. 2009. (EI).

[2]  L. R. Wang, Y. W Chiu, C. L. Hu, M. H. Tu, S. J. Jou and C. L. Lee, “A Reconfigurable MAC Architecture Implemented with Mixed-Vt Standard Cell Library,” IEEE Inter. Symp. Circuits and Systems, May 2008, pp. 3426 - 3429.

[3]  L. R. Wang, S. J. Jou and C. L. Lee,” A Well-Structured Modified Booth Multiplier       Design,” IEEE International Symp. on VLSI Design, Automation and Test, April 2008,     pp.85-88.

[4]  C. Y. Lin, C. L Hu, L. R. Wang, S. J. Jou, “Mixed-VTH (MVT) CMOS Circuit Design For Low Power Cell Libraries,” IEEE International SOC Conference, Sept. 2007.

 


Department of Electronics Engineering, National Chiao Tung University
1001 Ta-Hsueh Road, Hsinchu, Taiwan 30010, R.O.C. Tel: +886-3-5712121 ext: 54195