Publications list








(A) Referred Journal Articles (期刊論文)

[1]    C. Y. Yang, C W. Liu, and S. J. Jou, “A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-aid Systems,” IEEE/ACM Trans. Audio, Speech, and Language Processing, Vol.24, Issue 8, Aug 2016, pp.1380-1392.

[2]    C. F. Wu, W. C. Liu, C. C. Tsui, C. Y. Liu, M. S. Sie and S. J. Jou, “Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60 GHz Wireless OFDM/SC Receiver,” IEEE Transactions on Very Large Scale Integration Systems, April 2016.

[3]    C. W. Chang, K. Y. Lo, H. A. Ibrahim,Y. H. Chu, and S. J. Jou, “A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques,” IEICE Transactions on Electronics ,Vol. E99-C, No.4, April 2016, pp.4811-490.

[4]    C. W. Chang, K. Y. Chang, Y. H. Chu and S. J. Jou, “Near-threshold cell-based all-digital PLL with dynamic voltage scaling power management,” IET Electronics Letters, Volume 52, Issue 2, 21 January 2016, p. 109 – 111.

[5]    C. W. Chang, Y. H. Chu and S. J. Jou, “A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications,” IEICE Transactions on Electronics, Vol. E98.C, August 2015, p.882-891.

[6]    W. Q. He, Y.H. Chen; S. J. Jou, High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation,” IEEE Trans. Circuits Syst. I, Vol. 62, No.8, August. 2015, pp. 2052-2061.

[7]    C. Y. Lu, C. T. Chuang, S. J. Jou, M. H. Tu, Y. P. Wu, C. P. Huang, P. S. Kan, H. S. Huang,, K. D.  Lee, Y. S. Kao, “A 0.325V, 600kHz 40nm 72kb 9T Subthreshold SRAM with Aligned Boosted Write Word-Line and Negative Write Bit-Line Write-Assist,”  IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 5, May 2015, pp. 958-962.

[8]    M. C. Su, S. J. Jou, and W. Z. Chen, “A Low-Jitter Cell-Based Digitally-Controlled Oscillator with Differential Multi-Phase Outputs,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 4, April 2015, pp. 766-770.

[9]    M. C. Su; W. Z. Chen, P. S. Wu, Y. H. Chen, C. C. Lee and S. J. Jou,, “A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression,” IEEE Trans. Circuits Syst. I, Vol. 62, No.3, March 2015, pp. 743-751.

[10] W. C. Liu, T. C. Wei, Y. S. Huang, C. D. Chan and S. J. Jou, “All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad,” IEEE Trans. Circuits Syst. I, Vol. 62, No. 2, Feb. 2015, pp. 545-553.

[11] N. C. Lien, L.W. Chu, C. H. Chen, H. I. Yang, M. H. Tu, P. S. Kan, Y. J. Hu, C. T. Chuang, S. J. Jou, W. Huang, “A 40nm 512Kb Cross-Point 8T Pipeline SRAM with Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist,” IEEE Trans. Circuits Syst. I, Vol. 61, No. 12, Dec. 2014, pp. 3416-3425.

 

[12] S. J. Huang, S. G. Chen, M. Garrido, S. J. Jou, “Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures,” IEEE Trans. Circuits Syst. I,IEEE Trans. Circuits Syst. I, Vol. 61, No. 10, Oct. 2014, pp. 2869-2877.

[13] C. W. Wei, C. C. Tsai, Y. FanJiang, T. S. Chang and S. J. Jou, “Analysis and Implementation of Low Power Perceptual Multiband Noise Reduction for the Hearing Aids Application,” IET Proc. Circuits, Devices and Systems,.Vol.8, Issue:6, Nov. 2014, pp.516-525 (SCI, EI)

[14] Y. W Chiu, Y. H. Hu, M. H. Tu, J. K. Zhao, Y. H. Chu, S. J. Jou and C. T. Chuang, "40nm Bit-Interleaving 12T Subthreshold SRAM with Data-Aware Write-Assist, IEEE Trans. Circuits and Systems, part I, Vol. 61, No.9, Sept. 2014, pp.2578-2585.

[15] Y. FanChiang, C. W. Wei, Y. L. Meng, Y. W. Lin, S. J. Jou and T. S. Chang,” Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing,” IEEE/ACM Trans. Audio, Speech, and Language Processing,   Vol. 22, No.8, August 2014, pp.1248-1259.

[16]  Y. J. Chen, C. W. Wei, Y. FanChiang, Y. L. Meng, Y. C. Huang and S. J. Jou, “ Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application,”  IEEE Trans. Circuits and Systems, part I, Vol. 61, No. 2, Feb. 2014, pp.463-475.

[17] H. Y. Chen, W. K. Chang and S. J. Jou, “A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems,”  IEEE Trans. Circuits and Systems, part I. Vol. 60, No. 10, Oct. 2013, pp.2763-2773.

[18] W. C. Liu, F. C. Yeh, T. C. Wei, C. D. Chan and S. J. Jou , “A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band,”  IEEE Trans. Circuits and Systems, part I. Vol. 60, No. 10, Oct. 2013, pp.2730-2739.

[19] L. R. Wang, K. Y. Lo and S. J. Jou, "A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design," IEICE Trans. Electron, vol.E96-C, no.10, pp.1351-,1355, Oct. 2013.

[20] H. Y. Chen, J. N. Lin, H. S. Hu, and S. J. Jou, “STBC-OFDM Downlink Baseband Receiver for Mobile WMAN,” IEEE Trans. Very Large Scale Integration Systems, Vol.21 , No. 1  Jan. 2013, pp.43-54. (SCI, EI)

[21] C. Y. Lu, M. H. Tu, H. I Yang, Y. P. Wu, H. S. Huang, Y. J. Lin, K. D.  Lee, Y. S. Kao, C. T. Chuang, S. J. Jou and W. Hwang, “A 0.33V, 500KHz, 3.94μW 40nm 72Kb 9T Subthreshold SRAM with Ripple Bit-Line Structure and Negative Bit-Line Write-Assist,” IEEE Transactions on Circuits and Systems – Part 2: Vol.59 , No. 12  Dec. 2012, pp.863-867. (SCI, EI)

[22] Y. C. Lin, S. J. Jou, and M. T. Shiue, “High throughput extended incremental coefficient-lookahead filters based adaptive decision feedback equalizer," International Journal of Electrical Engineering, vol. 19, no. 3, 2012, pp. 115-126. (EI)

[23]  S. W. Yen, S. Y. Hung, C. L. Chen, H. C. Chang, S. J. Jou, and C. Y. Lee, ”5.79Gbps Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications, “IEEE Journal of Solid-State Circuits, Vol. 47, No. 9, July 2012, pp. 2246-2257. (SCI, EI)

[24] M. H. Tu, J. Y. Lin, M. C. Tsai, C. Y. Lu, Y. J. Lin, M. H. Wang, H. S. Huang, K. D. Lee, W. Shih, S. J. Jou, and C. T. Chuang, “A Single-Ended Disturb-Free 9T Subthreshold SRAM with Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing,”  IEEE Journal of Solid-State Circuits, Vol. 47, No. 6, June 2012, pp. 1469-1482. (SCI, EI)

[25] C. W. Wei, S. J. Su, T. S. Chang and S. J. Jou, “Sub-mW Noise Reduction for CIC Hearing Aids,” IEEE Trans. Very Large Scale Integration Systems, Vol.20 , No. 5  May. 2012, pp.937-947. (SCI, EI)

[26] Y. C. Lin, S. J. Jou, and M. T. Shiue, “Concurrent Look-Ahead Adaptive Decision Feedback Equalizer,” IET Proc. Circuits, Devices and Systems, Vol.1, January 2012, pp.52-62. (SCI, EI)

[27] L. R. Wang, M. H. Tu, S. J. Jou and C. L. Lee, “Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design,” IEICE Trans. on Electronics, Vol.E94-C, No.6, June 2011, PP.1112-1119. (SCI, EI)

[28] M. H. Tu, J. Y. Lin, M. C. Tsai, S. J. Jou and C. T. Chuang, “Single-Ended Subthreshold SRAM with  Asyrimmetcal Write/Read-Assist,” IEEE Trans. Circuits and Systems, part I, Vol.57 , No. 12  Dec. 2010, pp.3039-3047. (SCI, EI)

[29] H. Y. Chen, M. L. Ku, S. J. Jou and C. C. Huang, “A Robust Channel Estimator for High-Mobility,” IEEE Trans. Circuits and Systems, part I, Vol.57, No.4, April 2010, pp.925-936.  (SCI, EI)

[30] C. H. Liu, C. C. Lin, S. W. Yen, C. L Chen, H. C. Chang, C.Y. Lee, Y.S. Hsu and S. J. Jou, “Design of a Multimode QC-LDPC Decoder based on Shift-Routing Network (SRN),” IEEE Trans. Circuits and Systems, part II, Vol.56, No.9, Sept. 2009, pp.734-738.  (SCI, EI)

[31] T. C. Wei, W. C. Liu, C. Y. Tseng and S. J. Jou, “Low Complexity Synchronization Design of an OFDM Receiver for DVB-T/H,” IEEE Transactions on Consumer Electronics, Vol.55, No.2, May 2009, pp.408-413. (SCI, EI)

[32] T. C. Wei, W. C. Liu, and S. J. Jou, “A Jointed Mode Detection and Symbol Detection Scheme for DVB-T,” IEEE Transactions on Consumer Electronics, Vol.54, No.2, May 2008, pp.336-341. (SCI, EI)

[33] C. H. Liu, S. W. Yen, C. L. Chen, H. C. Chang, C. Y. Lee, Y. S. Hsu and S. J. Jou, “An LDPC Decoder Chip Based on Self-Routing Network for 802.16e Applications,” IEEE Journal of Solid-State Circuits, Vol.43, No.3, March 2008, pp.684-694. (SCI, EI)

[34] S. J. Jou, C. H. Lin, Y. H. Chen and Z. H. Li, “Design and Analysis of Digital Data Recovery Circuits Using Oversampling Technique,” IET Proc. Circuits, Devices and Systems, Vol.1, No.1, Feb. 2007, pp.93-102.(SCI, EI)

[35] M. C. Lin, H. Y. Chen and S. J. Jou, Design Techniques for High-Speed Multirate Multistage FIR Digital Filters,” International Journal of Electronics, Oct. 2006, pp.699-721.  (SCI, EI)

[36] H. Y. Chen, C. H. Lin and S. J. Jou, “DC-Balanced Low-jitter Transmission Code for 4-PAM Signaling,” IEEE Trans. Circuits and Systems, part II, Vol.53, No.9, Sept. 2006, pp.827-831.  (SCI, EI)

[37] C. H. Lin, Y. I. Wang and S. J. Jou, “Bit-Error-Rate Analysis for Clock and Data Recovery Based on Blind Oversampling Technique,” International Journal of Electrical Engineering, Vol.13, N0.3, August 2006, pp.219-228. (EI)

[38] C. H. Lin, C. N. Chen, Y. J. Wang, J. Y. Hsiao and and S. J. Jou, “Parallel Scrambler for High-Speed Applications,” IEEE Trans. Circuits and Systems, part II, Vol. 53,  No.7,  July 2006, pp.558-562.  (SCI, EI)

[39] Y. L. Tsao, W. H. Chen and S. J. Jou, “Hardware Nested Loop with Buffer of Parameterized and Embedded DSP core, “International Journal of  Electrical Engineering, Vol.13, N0.1, Feb., 2006. (EI)

[40] C. H. Lin, C. H., C. N. Chen and S. J. Jou, “Multi-Gigabit Pre-emphasis Design and Analysis for Serial Link,” IEICE Trans. on Electronics, Vol.E88-C, No.10, Oct. 2005, pp.2009-2019. (SCI, EI)

[41]  S. J. Jou, M. H. Tsai and Y. L. Tsao, ”Low-Error Reduced-Width Booth Multipliers for DSP Applications,” IEEE Trans. Circuits and Systems, part I, Vol.50, No.11,Oct. 2003, pp.1470-1474.  (SCI, EI)

[42] Y. L. Tsao, W. H. Chen, M. H. Tan, M. C. Lin and S. J. Jou, “Low Power Embedded DSP Core for Communication Systems,” EURASIP Journal on Applied Signal Processing, Dec. 2003, pp.1355-1370.(SCI, EI)

[43] M. C. Lin, C. L. Chen, D. Y. Shin, C. H. Lin and S. J. Jou, “ Multiplierless FIR Filter Architecture Synthesizer Based on CSD Code,” Journal of the Chinese Institute of Electrical Engineering, Vol.10, No.5, May 2003, pp.155-164. (EI).

[44] S. J. Jou, W. C. Cheng and Y. T. Lin, “Simultaneous Switching Noise Analysis and Low Bounce Buffer Design,” IEE Proceedings Circuits, Devices and Systems, Vol.148, No.6, Dec. 2001, pp.303-311. (SCI, EI)

[45]  S. J. Jou, S. H. Kuo, J. T. Chiu and V. Lin,Low Switching Noise and Load Adaptive Output Buffer Design Techniques,” IEEE Journal of Solid-State Circuits, Vol.36, No.8 August 2001, pp.1239-1249. (SCI, EI)

[46] C.C. Su, Y.T. Chen, and S.J. Jou, "Intrinsic Response for Analog Module Testing Using Analog Testability Bus," ACM Trans. on Design Automation of Electronic Systems, Vol. 6, No.2, April 2001, pp.226-243. (SCI, EI)

[47] C.C. Su and S.J. Jou, "Decentralized BIST for 1149.1 and 1149.5 Based Interconnects," Journal of Electronic Testing - Theory and Applications, Vol.15, No.3 Dec.1999, pp255-265. (SCI, EI)

[48] S. J. Jou, S. Y. Wu and C. K. Wang, “Low-Power Multirate Architecture for IF Digital Frequency Down Converter,” IEEE Trans. Circuits and Systems, part II, Vol.45, No.11, Nov. 1998, pp.1487-1494. (SCI, EI)

[49] S. J. Jou and T. L. Chen, “On-chip voltage down converter for low-power digital system,” IEEE Trans. Circuits and Systems, part II, Vol.45, No.5 May 1998, pp.617-625. (SCI, EI)

[50] C.C. Su, H.C. Lin, and S.J. Jou, “Design and Testing of a Mixed Signal Matched Filter for IS-95 CDMA Code Acquisition,” Proc. National Science Council, ROC, Vol. 22, No. 1, 1998, pp.95-102. (EI)

[51] S. J. Jou, M. F. Perng and C. C. Su, "Hierarchical techniques for symbolic analysis of electronic circuits," IEE Proceedings Circuits, Devices and Systems, Vol. 144, No. 3, June 1997, pp.167-177. (SCI, EI)

[52] S. J. Jou, K. F.  Liu and C. C. Su, "Circuits design optimization using symbolic approach," Journal of the Chinese Institute of Electrical Engineering, Feb. 1997, pp.51-60. (EI)

[53] S. J. Jou, C. Y. Chen, E. C. Yang and C. C. Su, "A pipelined Multiplier-Accumulator using a high-speed, low power static and dynamic full adder design, " IEEE Journal of Solid-State Circuits, Vol. 32, No. 1, January 1997, pp.114-118. (SCI, EI)

[54]  S. J. Jou and I-Yao Chung, “Low-power self-timed circuit design technique,” Electronics Letters, Vol.33 No.2, January 1997, pp.110-111. (SCI, EI)

[55]  S. J. Jou, J. H. Pan, W. H. Hsieh, C. C. Su, "Current and power waveforms simulators for CMOS circuits," Journal of the Chinese Institute of Electrical Engineering, May 1997, pp.141-148. (EI)

[56] W. H. Hsieh, S. J. Jou and C. C. Su, "Parallel event-driven MOS timing simulator on distributed memory multiprocessor, " IEE Proceedings Circuits, Devices and Systems, Vol.143, No.4, August 1996, pp.207-212. (SCI, EI)

[57]  S. J. Jou and C. C. Hung, "Hierarchical symbolic analysis of analog circuits," Proceedings of the National Science Council, Part A, Vol.17, No.4, July 1993, pp.301-313. (EI)

[58]  S. J. Jou, S. H. Chiou, Y. S. Tao and W. Z. Shen, "Event-driven incremental timing fault simulator," IEE Proc. Pt.G, Vol.140, No.1, Feb. 1993, pp.45-54. (SCI, EI)

[59]  W. Z. Shen, S. J. Jou and Y. S. Tao, "EMOTA-an event driven MOS timing simulator for VLSI circuits," IEE Proc. Pt.G, Vol.137, No.4, August 1990, pp.279-291. (SCI, EI)

[60]  C. W. Jen and S. J. Jou, "Design of one-dimension alsystolic systems for linear state equation," IEE Proc. Pt.G, Vol.137, No.3, June. 1990, pp.185-192. (SCI, EI)

[61]  S. J. Jou, C. W. Jen, "The design of a systolic system for linear state equation," IEE Proc. Pt.G, Vol.135, No.5, Oct. 1988, pp.211-218. (SCI, EI)

[62] S. J. Jou, W. Z. Shen,C. W.  Jen and C. L. Lee, "Simulatable timing model for MOS logic circuit", IEE  Proc. Pt.G, Vol.133, No.5, December 1987, pp.276-284. (SCI, EI)

[63] S. J. Jou, C. W. Jen, W. Z. Shen and C. L. Lee, "MOTA: a MOSFET timing simulator,"  IEE Proc. Pt.I, Vol.133, No.5, Oct. 1986, pp.193-199. (SCI, EI)

 



(B) Conference Proceedings (會議論文)

I. International Conference Proceedings (國際會議論文)

[1]       Y. W Chiu, Y. H. Hu, J. K. Zhao, S. J.  Jou and C. T. Chuang, “A Subthreshold SRAM with Embedded Data-Aware Write-Assist and Adaptive Data-Aware Keeper,” IEEE International Symp. On Circuits and Systems, May 2016

[2]       C. Y. Liu, M. S. Sie, E. W. J Leong, Y. C. Yao, W. C. Liu, and S. J.  Jou, Efficient Polyphase Network for 60GHz FBMC Baseband Receiver,IEEE International Symp. On Circuits and Systems, May 2016

[3]       Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, S. J.  Jou, “Error-resilient sequential cells with successive time borrowing for stochastic computing,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) March 2016, pp.1545-1549.

[4]       N. Preyss, C. Senning, A. Burg, W. C. Liu, C. Y. Liu, S. J.  Jou, “A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm,” IEEE Asian Solid-State Circuit Conference, Nov. 2015.

[5]       W. Q. He, Y. C. Lin, J. Y. Hung, and S. J. Jou, Full-Digital High Throughput Design of Adaptive Decision Feedback Equalizers Using Coefficient-Lookahead,” IEEE International ASICON Conference, Nov. 2015.

[6]       H. L. Davila, C. Y Liu, S. J. Huang, W. C. Liu, S. J. Jou and S. G. Chen, “A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems,” IEEE International System-on-Chip Conference, Sept. 8-11, 2015.

[7]       P. Aray, L. Y. Huang, W. C. Liu, H. T. Chang, C. W. Jen, C. F. Wu and S. J. Jou, “Gb/s Prototyping of 60GHz Indoor Wireless SC/OFDM Transmitter and Receiver on FPGA Demo System”, IEEE Int. Symp. on consumer Electronics, June 2015.

[8]       C. H. Hong, Y. W. Chiu, J. K. Zhao, S. J. Jou, W. T. Wang and R. Lee, “A 28nm 36 Kb High Speed 6T SRAM with Source Follower PMOS Read and Bit-Line Under-Drive,” IEEE International Symp. On Circuits and Systems, May 2015

[9]       L. Y. Huang, Chia-Yi Wu,  C. Y. Liu, W. C. Liu, C. F. Wu, S. J. Jou, “A 802.15.3c/802.11ad Dual Mode Phase Noise Cancellation for 60 GHz Communication Systems,”  IEEE International Symp. on VLSI Design, Automation and Test, April 2015.

[10]   J. K. Zhao, Y. W. Chiu, S. J. Jou, and Y. H. Chu, “Subthreshold SRAM Macro Design with Pulse-Controlled Dynamic Voltage Scaling (PC-DVS),” IEEE International SOC Design Conference, Nov. 2014. (cadence awards)

[11]   C. K. Chung, C. Y. Lu, Z. H. Chang, S. J. Jou, C. T. Chuang, M. H. Tu, Y. H. Chen, Y. J. Hu , P. S. Kan, H. S. Huang, K. D. Lee and Y. S. Kao, “A 40nm 256kb 6T SRAM with Threshold Power-Gating, Low-Swing Global Read Bit-Line, and Charge-Sharing Write with Vtrip-Tracking and Negative Source-Line Write-Assists,” IEEE International System-on-Chip Conference, Sept. 2-5, 2014.

[12]   C. H. Hong, Y. W. Chiu, J. K. Zhao, S. J. Jou  W. T. Wang and R. Lee “A Low Power Charge Sharing Hierarchical Bitline and Voltage-Latched Sense Amplifier for SRAM Macro in 28nm CMOS Technology,” IEEE International System-on-Chip Conference, Sept. 2-5, 2014.

[13]   W. C. Liu, F. C. Yeh, C. Y. Wu, T. C. Wei, Y. S. Huang, T. Y. Liu, S. J. Huang, C. D Chan, S. J. Jou and S. G. Chen, “A 802.15.3c/802.11ad Compliant SC/OFDM Dual-Mode Baseband Receiver for 60 GHz Communication,” IEEE International Symp. On Circuits and Systems, May 2014, pp. 1006–1009.

[14]   K. C. Chang, S. C. Luo, C. J. Huang, C. W. Liu, Y. H. Chu, and S. J. Jou, “An ultra-low voltage hearing aid chip using variable-latency design technique,” IEEE International Symposium on Circuits and Systems, May 2014, pp. 2543–2546.

[15]   M. C. Su, W. Z. Chen, P. S. Wu, Y. H. Chen, C. C. Lee, and S. J. Jou, “A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression,”  IEEE Custom Integrated Circuits Conference, Sept. 2013

[16]   Y. C. Huang, Y. FanChiang, and S. J. Jou, “A Pitch Based VAD Adopting Quasi-ANSI 1/3 Octave Filter Bank with 11.3 Ms Latency for Monosyllable Hearing Aids,” in Proc. IEEE Workshop on Signal Processing System, Oct. 2013.

[17]   C. Y. Yang, W. S. Chou, K. C. Chang, C. W. Liu, T. S. Chi, and S. J. Jou, “Spatial-Cue-Based Multi-Band Binaural Noise Reduction for Hearing Aids,” Proc. IEEE Workshop on Signal Processing System, Oct. 2013.

[18]   W. N. Liao, N. C. Lien, C. S. Chang, L. W. Chu, H. I. Yang, C. T. Chuang, S. J. Jou, W. Hwang, M. H. Tu, H. S. Huang, J. H. Wang, P. S. Kan and Y. J. Hu, “A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control,” Proc. 2013 IEEE International System-on-Chip Conference (SOCC), Erlangen, Germany, Sept. 4-6, 2013, pp. 110-115.

[19]   Y. W. Chiu, Y. H. Hu, M. H. Tu, J. K. Zhao, S. J. Jou and C. T. Chuang, “A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM hwit Data-Aware Write-Assist,” in Proc. IEEE Int. Symp Low Power Electronics and Design, 2013.

[20]   C. S. Chang, H. I. Yang, W. N. Liao, Y. W. Lin, N. C. Lien, C. H. Chen, C. T. Chuang, W. Hwang, S. J. Jou, M. H. Tu, H. S. Huang, Y. J. Hu, P. S. Kan, C. Y. Cheng, W. C. Wang, J. H. Wang, K. D. Lee, C. C. Chen and W. C. Shih, “A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist,” 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, May 19-23, 2013, pp. 1468-1471.

[21]   W. C. Liu, F. C. Yeh, T. C. Wei, Y. S. Huang, T. Y. Liu, S. J. Huang, C. D Chan, S. J. Jou and S. G. Chen, “A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c,” IEEE International Symp. On Circuits and Systems (ISCAS), May 2013.

[22]   C. D. Chan, W. C. Liu, C. H. Yang and S. J. Jou, “Power and Area Reduction in Multi-Stage Addition Using Operand Segmentation,” IEEE International Symp. on VLSI Design, Automation and Test, April 2013.

[23]   S. C. Wang, G. C. Lin, Y. W. Lin, M. C. Tsai, Y. W. Chiu, S. J. Jou, C. T. Chuang, N. C. Lien, W. C. Shih, K. D. Lee and J. K. Chu, “Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM,” Proc. 2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, Taiwan, Dec. 2-5, 2012 , pp. 116-119.

[24] J.C. Sun, J. L. Chen, S. C. You, S. J. Jou, and T. H. Sang, ”A 80-uW 2-Mb/s Transceiver for Human Body Channel Binaural Communication,” IEEE Biomedical Circuits and Systems Conference, Nov. 2012.

[25] H. Y. Yang, C. W. Lin, H. H. Chen, M. C. T, M. H. Tu, S. J. Jou and C. T. Chuang, “Testing strategies for a 9T sub-threshold SRAM,” IEEE International Test Conference (ITC), paper 14-2, pp.1-10, 2012.

[26]   G. C. Lin, S. C. Wang, Y. W. Lin, M. C. Tsai, C. T. Chuang , S. J. Jou, N. C. Lien, W. C. Shih, K. D. Lee, and J. K. Chu, “An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array,” IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012.

[27]   H. I. Yang, Y. W. Lin, M. C. Hsia, G. C. Lin, C. S. Chang, Y. N. Chen, C. T. Chuang, W. Hwang, S. J. Jou, N. C. Lien, H. Y. Li, K. D. Lee, W. C. Shih, Y. P. Wu, W. T. Lee, and C. C. Hsu, “High-Performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder,” IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012.

[28]   M. C. Tsai, Y. W. Lin, H. I Yang, M. H. Tu, W. C. Shih, N. C. Lien, K. D. Lee,  S. J. Jou, C. T. Chuang and W. Hwang, “Embedded SRAM Ring Oscillator for In-Situ Measurement of NBTI and PBTI Degradation in CMOS 6T SRAM Array,” IEEE International Symp. on VLSI Design, Automation and Test, April 2012.

[29]   Y. W. Lin, M. C. Tsai, H. I Yang, G. C. Lin, S. C. Wang, C. T. Chuang, S. J. Jou, W. Hwang, N. C. Lien, K. D. Lee and W. C. Shih, “An All-Digital Read Stability and Write Margin Characterization Scheme for CMOS 6T SRAM Array,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 23-25, 2012

[30]   C. W. Chang, S. J. Jou and Y. H. Chu,  0.5 VDD Digitally Controlled Oscillators Design with Compensation Techniques for PVT Variations,” IEEE International ASICON Conference, Oct. 2011.

[31]   M. C. Su, S. J. Jou,” Digitally-Controlled Cell-based Oscillator With Multi-Phase Differential Outputs,” IEEE International ASICON Conference, Oct. 2011.

[32]    H. I. Yang, S. C. Yang, M. C. Hsia, Y. W. Lin, Y. W. Lin, C. H. Chen, C. S. Chang,  G. C. Lin, Y. N. Chen, C. T. Chuang, W. Huang, S. J. Jou, N. C. Lien, H. Y. Li,  K. D. Lee, W. C. Shih, Y. P. Wu, W. T. Lee, C. C. Hsu, “A High-Performance Low VMIN 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control,” Proc. 2011 IEEE International SOC Conference (SOCC), Taipei, Taiwan, Sept. 2011, pp. 197-200.

[33]   M. H. Tu, S. J. Jou and C. T. Chuang, “A 72Kb Single-Ended Disturb-Free Subthreshold SRAM with Cross-Point Data-Aware Write Word-Line, Negative Bit-Lane, and Adaptive Read Operation Timing Tracing, ” The 2011 Subthreshold Microelectronics Conference, Sept. 2011.

[34]   Y. W. Chiu, J. Y. Lin, M. H. Tu, S. J. Jou and C. T. Chuang, “8T Single-ended Sub-threshold SRAM Cell with Data-aware Write Operation,” IEEE International Symposium on Low Power Electronics and Design, August 2011, pp.169-175.

[35]   Y. Fan-Chiang, C.W.Huang, T.H.Chi and S. J. Jou, “Low power InfomaxICA with compensation strategy for binaural hearing-aid,” IEEE Inter. Symp. Circuits and Systems, May 2011, pp. 2083 - 2086.

[36]    Y. S. Huang, W. C. Liu and S. J. Jou, “Design and Implementation of Synchronization Detection for IEEE 802.15.3c,” IEEE International Symp. on VLSI Design, Automation and Test, April 2011, pp. 1-4.

[37]   F. C. Yeh, T. Y. Liu, T. C. Wei, W. C. Liu, and S. J. Jou, “A SC/OFDM Dual Mode Frequency-Domain Equalizer for 60GHz Multi-Gbps Wireless Transmission,IEEE International Symp. on VLSI Design, Automation and Test, April 2011, pp.1-4.

[38]   C. W. Wei, C. C. Tsai, T. S. Chang and S. J. Jou,  Perceptual Multiband Spectral Subtraction for Noise Reduction in Hearing Aids,” IEEE Asia Pacific Conference on Circuits and Systems, Dec. 2010, pp.692-695.

[39]   C. W. Wei,  Y.T. Kuo,  K. C. Chang,  C. C. Tsai,  J. Y. Lin,  Y. FanJiang,  M. H. Tu, C. W. Liu,  T. S. Chang  and  S. J. Jou, “A Low-Power Mandarin-Specific Hearing Aid Chip,” IEEE Asian Solid-State Circuit Conference, Nov. 2010, pp.1-4.

[40]   S. Y. Hung, S. W. Yen, C. L. Chen, H. C. Chang, S. J. Jou, and C. Y. Lee, “A 5.7Gbps Row-Based Layered Scheduling LDPC Decoder for IEEE 802.15.3c Applications,” IEEE Asian Solid-State Circuit Conference, Nov. 2010, pp.1-4.

[41]   Y. J. Chen, C. W. Wei, Y. L. Meng and S. J. Jou, “Low Computational Complexity Pitch Based VAD for Dynamic Environment in Hearing,” IEEE 2010 International Conference on Bio-Inspired Systems and Signal Processing (ICBSSP), Oct. 2010.

[42]   W. C. Liu, C. H. Lin, S. J. Jou, H. W Lu, C. C. Su, K. W. Hong, K. H. Cheng , S. W. Yang, M. H Sheu, “A Micro-Network on Chip with 10-Gb/s Transmission Link,” IEEE Asian Solid-State Circuit Conference, Nov. 2009,pp.277-280.

[43]   C. H. Lin, Y. Y. Huang, S. R Li, Y. P. Cheng and S. J. Jou, “A Low-jitter Spread Spectrum Clock Generator with Phase-rotation Algorithm for 6Gbps Clock and Data Recovery,” IEEE International ASICON Conference, Oct. 2009, pp.387-390.

[44]   J. Y. Lin, M. H. Tu, M. C. Tsai, S. J. Jou and C. T. Chuang, “Asymmetrical Write-Assist for Single-End SRAM Operation,” IEEE International SOC Conference, Sept. 2009, pp.101-104. (EI)

[45]   S. W. Yen, M. C. Hu, C. L. Chen, H. C. Chang, S. J. Jou, and C. Y. Lee, “A 0.92mm2 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application,” IEEE Custom Integrated Circuits Conference, Sept. 2009, pp.191-194.

[46]   Y. C. Lin, M. T. Shiue and S. J. Jou, “10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop,” IEEE Inter. Symp. Circuits and Systems, May 2009, pp. 1839 - 1912. (EI)

[47]   H. S. Hu, H. Y. Chen and S. J. Jou, “A Novel FFT Architecture for DFT-based Channel Estimation in IEEE 802.16e,” IEEE International Symp. on VLSI Design, Automation and Test, April 2009, pp.150-153. (EI)

[48]   T. C. Wei, W. C. Liu, C. Y. Tseng, S. S. Long, S. J. Jou, and M. T. Shiue, “A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization,” IEEE Custom Integrated Circuits Conference, Sept. 2008, pp.351-354.(EI)

[49]   L. R. Wang, Y. W Chiu, C. L. Hu, M. H. Tu, S. J. Jou and C. L. Lee, “A Reconfigurable MAC Architecture Implemented with Mixed-Vt Standard Cell Library,” IEEE Inter. Symp. Circuits and Systems, May 2008, pp. 3426 - 3429. (EI)

[50]   J. N. Lin, H. Y. Chen, T. C. Wei and S. J. Jou, “Symbol and Carrier Frequency Offset Synchronization for IEEE802.16e,” IEEE Inter. Symp. Circuits and Systems, May 2008, pp. 3082 - 3085. (EI)

[51]   L. R. Wang, S. J. Jou and C. L. Lee,” A Well-Structured Modified Booth Multiplier Design,” IEEE International Symp. on VLSI Design, Automation and Test, April 2008, pp.85-88. (EI)

[52]   J. Y. Lin, C. L Hu, L. R. Wang, S. J. Jou, “Mixed-VTH (MVT) CMOS Circuit Design For Low Power Cell Libraries,” IEEE International SOC Conference, Sept. 2007. (EI)

[53]   C. S. Lin, Y. C. Lin, S. J. Jou and M. T. Shiou, “Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System,” IEEE Custom Integrated Circuits Conference, Sept. 2007. (EI)

[54]   W. C. Liu, T. C. Wei and S. J. Jou, Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H,” IEEE Inter. Symp. Circuits and Systems, May 2007, pp.2092-2095. (EI)

[55]   C. M. Chu, C. H. Lin and S. J. Jou, “A 6Gbps Serial Transmitter with Pre-Emphasis,” IEEE International Symp. on VLSI Design, Automation and Test, April 2007, pp.73-76. (EI)

[56]   C.Y. Tseng, T.C. Wei, W.C.  Liu and S. J. Jou, “Low Power and Power Aware Design for DVB-T/H Baseband Inner Receiver,” IEEE International Symp. on VLSI Design, Automation and Test, April 2007, pp.204-207. (EI)

[57]   W.C.  Liu, T.C. Wei and S. J. Jou, “Two-Stage Scattered Pilot Synchronization with Channel Estimation ScatteredPilots Pre-Filling for DVB-T/H,” IEEE International Symp. on VLSI Design, Automation and Test, April 2007, pp.200-203. (EI)

[58]   H. Y. Chen and S. J. Jou, “Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-power and High-performance Applications,” IEEE Int. Conf. Acoustics, Speech, and Signal Processing, April 2007, pp. III-1473–1476. (EI)

[59]   T. Z. Wei, S. J. Jou and M. T. Shieu, “Memory Reduction ICFO Estimation Architecture for DVB-T,” IEEE Inter. Symp. Circuits and Systems, May 2006, pp.3406-3409

[60]   J. H. Huang, C. H. Lin and S. J. Jou, Adaptive Quadrature Clock Generator,”  IEEE International Symp. on VLSI Design, Automation and Test, April 2006, pp.203-206. (EI)

[61]   C. H. Lin and S. J. Jou, “4/2 PAM Pre-emphasis Transmitter with Combined Driver and Mux,” IEEE Asian Solid-State Circuit Conference, Nov. 2005, pp.189-192.

[62]   S. J. Jou, C. H. Lin, C. N. Chen and Y. J. Wang, “Multi-Gigabit Serial Link Transmitter- Off-Chip and On-Chip,” IEEE Emerging Information Technology Conference, August 2005, pp.75-78.

[63]   S. J. Jou, . C. H. Lin and Y. I. Wang, “A 12.5 Gbps CMOS Input Sampler for Serial Link Receiver Front End, IEEE Inter. Symp. Circuits and Systems, May 2005, pp.V293-V296.

[64]   C. H. Lin, C. N. Chen and S. J. Jou, “Adaptive On-Die Termination Resistors for High-Speed Transceiver,” IEEE International Symp. on VLSI Design, Automation and Test, April 2005,  pp.96-99.

[65]   Y. L. Tsao, J. X. Teng, M. C. Lin and S. J. Jou, “Low Power Correlator of DSP Core for Communication System,” IEEE Asia-Pacific Conference on Circuits and Systems, Dec. 2004, pp.217-220.

[66]   Y. L. Tsao, Y. C. Lin, W. H. Chen, B. S. Huang and  S. J. Jou, “A Module Generator for Parameterized DSP Core,”  IEEE Asia-Pacific Conference on Circuits and Systems, Dec. 2004, pp.361-364.

[67]   Y. L. Tsao, W. H. Chen and S. J. Jou, “Buffering Hardware Nested Loop of Parameterized and Embedded DSP Core,”  The 12th Workshop on Synthesis and System Integration of Mixed Information technologies, Oct. 2004, pp.262-265

[68]   S. J. Jou, K. Y. Jheng, H. Y. Chen H. Y. Chen, and A. Y. Wu, “Multiplierless Multirate Decimator/Interpolator Module Generator,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), Aug. 2004 pp. 58-61.

[69]   H. Y. Chen, C. H.  Lin and S. J. Jou, “Low-jitter Transmission Code for 4-PAM Signaling in Serial Links,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), Aug. 2004, pp. 334-337.

[70]   S. J. Jou, K. Y. Jheng, A. Y. (Andy) Wu,” A Design Flow for Multiplierless Linear-Phase FIR Filters: From System Specification to Verilog code,” IEEE Inter. Symp. Circuits and Systems, May 2004, pp.V293-V296.

[71]   C. H. Lin, C. N. Chen, C. H. Tsai and S. J. Jou, “4/2 PAM Serial Link Transmitter with tunable Pre-Emphasis,” IEEE Inter. Symp. Circuits and Systems, May 2004, PP.I952-I955.

[72]   Y. L. Tsao, W. H. Chen, M. C. Lin and S. J. Jou, “HardWare Nested Looping of Parameterized and Embedded DSP Core,” IEEE International SOC Conference, Sept, 2003, pp.49-52.

[73]   S. J. Jou, C. H. Lin, T. H. Chen and Z. H. Li, “Module Generator of Data Recovery Circuits Using Oversampling Technique,” IEEE International SOC Conference, Sept, 2003, 95-98.

[74]   Y. L. Tsao, M. H. Tan, J. X. Teng and S. J. Jou, “Parameterized and Low Power DSP Core for Embedded Systems,” IEEE Inter. Symp. Circuits and Systems, May 2003, pp.V265-V268.

[75]   C. H. Lin, C. H. Wang and S. J. Jou, “5Gbps Serial Link Transmitter with Pre-emphasis,” IEEE Asia and South Pacific Design Automation Conference, Jan. 2003, pp.795-800.

[76]   J. S. Liu, I. H. Chen, Y. C. Tsai and S. J. Jou, “ Low-Power Digital CDMA Receiver,” IEEE Asia and South Pacific Design Automation Conference, Jan. 2003, pp.581-582.

[77]   C. H. Lin , I. C Yao , C. C. Kuo and S. J. Jou, “2.5Gbps CMOS Laser Diode Driver with APC and Digitally Controlled Current Modulation,” The Third IEEE Asia Pacific Conference on ASICs, August 2002, pp.77-80.

[78]   Y. L. Tsao, M. C. Chung and S. J. Jou,Low-Noise Skewed Output Buffer Using DLL,” The Third IEEE Asia Pacific Conference on ASICs, August 2002, pp.279-282.

[79]   S. J. Jou, H. Y. Lin, M. T. Shiau, J. Y. Heh and C. K. Wang, “Design of Carrier Recovery for QAM/VSB Dual Mode,” IEEE International Conference of Communications, Circuits and Systems, June 2002, pp.1535-1539.

[80]   S. J. Jou, H. P. Lee, Y. T. Chen, M. H. Tan and Y. L. Tsao, “ An Embeded DSP Core for Wireless Communication,” IEEE Inter. Symp. Circuits and Systems, May 2002, pp.524-527.

[81]   M. H. Tsai, Y. T. Chen, W. S. Cheng, J. X. Teng and S. J. Jou, “ Sub-word and Reduced-Width Booth Multipliers for DSP Applications, “IEEE Inter. Symp. Circuits and Systems, May 2002, pp.575-578.

[82]   S. J. Jou, S. H. Kuo, J. T. Chiu, C. King, C. H. Lee and Tim Liu,  “A Serial Link Transceiver for USB2 High-Speed Mode,” IEEE Inter. Symp. Circuits and Systems, May 2001, IV-72-IV-75.

[83]   M. C. Lin, C. L. Chen, D. Y. Shin, C. H. Lin and S. J.  Jou, Low-Power Multiplierless FIR Filter Synthesizer Based on CSD Code,” IEEE Inter. Symp. Circuits and Systems, May 2001, pp.IV-666-IV-669.

[84]   S. J.  Jou and Hui-Hsuan Wang, “Fixed-Width Multiplier for DSP Application,” IEEE International Symposium on Computer Design, Sept. 2000, pp318-322.

[85]   S. J. Jou, Shu-Hua Kuo, Jui-Ta Chiu and Victor Lin, “Adaptive AC/DC Output Buffer with Reduced Ground Bounce and Output Ringing,” The second IEEE Asia Pacific Conference on ASICs, Cheju, Korea, August 2000, pp.65-68.

[86]   C. F. Wu, M. T. Shiue, C. C. Huang and S. J. Jou, “QAM/VSB dual mode equalizer design and implementation,” The first IEEE Asia Pacific Conference on ASICs, Seoul, Korea, August 1999, pp.323-326

[87]   M. C. Lin, H. Y. Lin, C. L. Chen and S. J. Jou, “Digitally programmable DC-DC Voltage Down Converter,” The first IEEE Asia Pacific Conference on ASICs, Seoul, Korea, August 1999, pp.367-370

[88]   S. J. Jou, C. H. Kuo, M. T. Shiau, J. Y. Heh and C. K. Wang, “VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode,” International Symp. on VLSI Technology, Systems and Applications, Taipei, R. O. C. June 1999,  pp.159-162.

[89]   S. J. Jou, S. Y. Wu and C. K. Wang, “Low-power multirate IF digital frequency down converter,” International Symp. on VLSI Technology, Systems and Applications, Taipei, R. O. C. June 1999,  pp.231-234.

[90]   S. J. Jou, Ya-Lan Tsao and I-Ying Yang, “An all digital phase-locked loop with modified binary search of frequency acquisition,” 5th IEEE International Conference on Electronics, Circuits and Systems, Sept 1998.

[91]   S. J. Jou, W. C. Cheng and Y. T. Lin, “Simultaneous Switching Noise Analysis and Low Bouncing Buffer Design," IEEE Custom Integrated Circuits Conference, May 1998, pp.25.5.1-25.5.4.

[92]   C. C. Su, Y-T. Chen, S. J. Jou, “Parasitic effect removal for analog measurement in p1149.4 environment, “ Proc. 1997 Int’l Test Conference, Nov.1997, pp.499-508.

[93]   S. J. Jou and Tsu-Lin Chen, “ On-chip voltage down converter for LV/LP digital system, “ IEEE Inter. Symp. Circuits and Systems, June 1997, pp.1996-1999.

[94]    S. J. Jou and I-Yao Chung, “low-power global Asynchronous local synchronous design using self-timed circuit technology,” IEEE Inter. Symp. Circuits and Systems, June 1997, pp.1808-1811.

[95]    C. C. Su, H. C. Lin and S. J. Jou, “Mixed signal design of cascadable matched filters,” IEEE Inter. Symp. Circuits and Systems, June 1997, pp.2108-2111.

[96]   S. J. Jou, Tsan-I Hsu and C. K. Wong, “Low-voltage low-power IF-baseband digital down converter,” International Symp. on VLSI Technology, Systems and Applications, Taipei, R. O. C. June 1997,  pp.270-274.

[97]   C. C. Su, Y-T. Chen, S. J. Jou, “Structural approach for performance driven ECC circuit synthesis,” Asia and South Pacific Design Automation Conference, Jan. 1997, pp.89-94.

[98]   C. C. Su, Y-T. Chen, S. J. Jou and Y-T. Ting, “Metrology for analog module testing using analog testability bus,” IEEE International Conference on CAD, November ,1996, pp.594-599.

[99]    S. C. Yin, C. C. Su, M. T. Shiue, L. Y. Huang, C. K. Wang, S. J. Jou and W. I. Way, "A new VSB modulation technique and shaping filter design," IEEE Inter. Symp. Circuits and Systems, June 1996.

[100]  C. C. Su, S. J. Jou and Y. T. Ting, "Decentralized BIST for 1149.1 and 1149.5 based interconnects", The European Design and Test Conference, March. 1996, pp.120-125.

[101] C. C. Su, S. S. Chiang and S. J. Jou, "Impulse response fault model and fault extraction for functional level analog circuit Diagnosis," IEEE International Conference on CAD, November ,1995, pp.631-636.

[102]  S.J. Jou, C. Y. Chen, E. C. Yang and C. C. Su, "A pipelinning multiplier-accumulator using a high speed, low power static and dynamic full adder design," IEEE Custom Integrated Circuits Conference, May 1995, pp.27.6.1-27.6.4.

[103]  W. H. Hsieh, S. J.  Jou and C. C. Su, "A parallel Event-driven MOS timing simulator for distributed-memory multiprocessor," IEEE Inter. Symp. Circuits and Systems, May 1995, pp.1396-1399.

[104] J. Jou, K. F. Liu and C. C. Su, "Circuits design optimization using symbolic approach," IEEE Inter. Symp. Circuits and Systems, May 1995, pp.574-577.

[105] C. C. Su, K. C. Hwang and S. J. Jou, "An IDDQ Based built-in concurrent test technique for interconnects in a boundary scan environment", Proc. IEEE Int'l Test Conf. , Oct. 1994.

[106] J. Jou, M. F. Perng, C. C. Su and C. K. Wang, "Hierarchical Techniques for symbolic analysis of large electronic circuits" IEEE Inter. Symp. Circuits and Systems, June 1994, pp.21-24.

[107]  R. Saleh, S. J. Jou, D. Overhauser, X. Xu and Y. Wang, "Benchmark Circuits for Mixed-Mode Simulators", IEEE Custom Integrated Circuits Conference, May 1994, pp.21.1.1-21.1.8.

 

[108]  S.J. Jou and C. C. Hung, "An efficient determinant approach to symbolic function generator for analog circuits," 35th Midwest Symp. on Circuits and Systems, Washington, August 1992, pp. 827-830.

[109]  S. J. Jou, W. Z. Shen and S. H. Chiou, "An event-driven incremental timing fault simulator," International Symp. on VLSI Technology, Systems and Applications, Taipei, R. O. C. May 1991,  pp.424-427.

[110]  S. J. Jou, C. W. Jen and W. Z. Shen, "Parallelism of circuit simulation on array processor," IEEE Inter. Symp. Circuits and Systems, June 1991, pp.2725-2728.

[111]  S. J. Jou, C. W. Jen and W. Z. Shen, "A systolic array system for linear state equation," IEEE Inter. Conf. Systolic Array, May 1988, pp.275-284

[112]  S. J. Jou, W. Z. Shen, C. W. Jen and C. L. Lee, "A robust MOS timing simulator," International Symposium on VLSI Technology, Systems and Applications, Taipei, R.O.C., May 13-15, 1987, pp.119-123.

[113]  S. J. Jou, C. W. Jen, W. Z. Shen and C. L. Lee, "MOTA:a MOSFET timing simulator," IEEE International Conference on CAD, November , 1984, pp.10-12.

 

II. Domestic Conference Proceedings (國內會議論文)

[1]  C. W. Wei; Y. L. Meng; B. C. Huang; Y. R. Hung and S. J. Jou, “A Rapid Prototyping of Mandarin Hearing Aid Prescription,” Proc. 19th VLSI Design/CAD Symposium, Aug. 2008, pp. S17-6.

[2]  H. S. Hu, H. Y. Chen and S. J. Jou, “A Multiple Sequence Data In and Multiple Sequence Data Out FFT/IFFT Architecture for DFT-based Channel Estimation in IEEE 802.16e,” Proc. 19th VLSI Design/CAD Symposium, Aug. 2008, pp. S7-6

[3]  J. Y. Lin, L. R. Wang, C. L. Hu and S. J. Jou, “Mixed-Vth (MVT) CMOS Circuit Design For Low Power Cell Libraries,” Proc. 18th VLSI Design/CAD Symposium, Aug. 2007, pp.459-462

[4]  C. S. Lin, Y. P. Cheng, Y. Y. Huang, and S. J. Jou, “6 Gb/s Digitally Phase Adjusted Clock Data Recovery for Spread Spectrum Clock,” Proc. 18th VLSI Design/CAD Symposium, Aug. 2007, pp.668-671.

[5]  J. N. Lin, H. Y. Chen and S. J. Jou, “Symbol and Integer Carrier Frequency Offset Synchronization for IEEE802.16e,” Proc. 18th VLSI Design/CAD Symposium, Aug. 2007, pp.601-604.

[6]  C. S. Lin, Y. Y. Huang, S. R. Li, Y. P. Cheng and S. J. Jou, “A Low-jitter Phase-rotation Spread Spectrum Clock Generator for Serial ATA 6Gbps Clock and Data Recovery,” Proc. 18th VLSI Design/CAD Symposium, Aug. 2007, pp.652-655.

[7]  C. S. Lin, S. J. Jou, M. T. Shieu, “All Digital Adaptive Decision Feedback Equalizer (ADFE)for 10GBase-LX4 Ethernet System,” Proc. 17th VLSI Design/CAD Symposium, Aug. 2006, pp.B1-3.

[8]  W. C. Liu, T. Z. Wei, S. J. Jou, “Two-Stage Scattered Pilot Synchronization with Pilots Pre-Filling Scheme and Fast Demapping Scheme for DVB-T/H,” Proc. 17th VLSI Design/CAD Symposium, Aug. 2006, pp.B1-11

[9]  W. C. Liu, T. Z. Wei, S. J. Jou, “Mode/GI Detection and Coarse Symbol Synchronization Architecture Design for DVB-T/H,” Proc. 17th VLSI Design/CAD Symposium, Aug. 2006, pp.B1-7

[10] C. H. Chuang, C. H. Lin, S. J. Jou, “A Low-jitter Programmable Spread Spectrum Clock Generator for Serial ATA 6Gbps,” Proc. 17th VLSI Design/CAD Symposium, Aug. 2006, pp.C1-4

[11] C. M. Chu, C. H. Lin and S. J. Jou, “6Gbps Serial ATA Transmitter with Tunable Pre-Emphasis,” Proc. 17th VLSI Design/CAD Symposium, Aug. 2006, pp.C3-10

[12] C. Y. Tseng, T. Z. Wei, S. J. Jou, “Low Power Design and Implementation for DVB-T/H Baseband Inner Receiver,” Proc. 17th VLSI Design/CAD Symposium, Aug. 2006, pp. B1-13.

[13] L. R. Wang, S. J. Jou, C. L. Lee, “A Reconfigurable MAC Architecture with Modified Booth Multiplier,” Proc. 17th VLSI Design/CAD Symposium, Aug. 2006, pp.A2-10

[14] P. H. Huang, Y. L. Tsao, Y. C Lin, and S. J. Jou, “Stream Based I/O of Embedded DSP Core,  Proc. 16th VLSI Design/CAD Symposium, Aug. 2005, pp. A2-3.

[15] C. N. Chen, Y. J. Wang, J. Y. Hsiao, C. H Lin and S. J. Jou,, “ Parallel Scrambler With DET Register of Embedded XOR, Proc. 16th VLSI Design/CAD Symposium, Aug. 2005, pp. P1-28.

[16]  T. Z Wei, M. T. Shieu and S. J. Jou, “Memory Reduction ICFO Estimation Architecture for DVB-T,” Proc. 16th VLSI Design/CAD Symposium, Aug. 2005, pp. P2-35.

[17] Y. L. Tsao, J. X. Teng, M. C. Lin and and S. J. Jou, “Low Power Correlator of DSP Core for Communication System,” Proc. 14th VLSI Design/CAD Symposium, Aug. 2003, pp. 249-252

[18] K. Y. Cheng and S. J. Jou, “Multiplierless Multistage Multirate FIR Digital Decimator Module Generator,” Proc. 14th VLSI Design/CAD Symposium, Aug. 2003, pp.545-548

[19] S. J. Jou, C. H. Lin, Y. H. Chen and Z. H. Li, “Module Generator of Data Recovery for Serial Link Receiver,” Proc. 14th VLSI Design/CAD Symposium, Aug. 2003, pp.513-516.

[20] W. H. Chen, Y. L. Tsao, P. H. Huang and S. J. Jou, “Parameterized Hardware looping of DSP Core,” Proc. 14th VLSI Design/CAD Symposium, Aug. 2003, pp.97-100

[21] Y. L. Tsao, M. C. Lin, J. X. Teng, M. H. Tan, S. J. Jou, “Parameterized DSP with Co-Function for Communication System Application,” Proc. 13th VLSI Design/CAD Symposium, Aug. 2002, pp. 371-374.

[22] C. C. Kuo, C. H. Lin, Y. H. Chen, S. J. Jou, “All-Digital Data Recovery Using An Oversampling Technique,” Proc. 13th VLSI Design/CAD Symposium, Aug. 2002, pp. 419-422.

[23] I. C. Yao, C. C. Kuo, W. Z. Chen and S. J. Jou, “1.25 Gbps Laser Diode Driver,” Proc. 12th VLSI Design/CAD Symposium, Aug. 2001, pp. 240-243.

[24] S. J. Jou, Jui-Ta Chiu Shu-Hua Kuo and Victor Lin, “Adaptively Separated SSN Output Buffer with Reduced Ground Bounce and Output Ringing,” Proc. 11th VLSI Design/CAD Symposium, Aug. 2000, pp. 141-144.

[25] M. C. Chung and S. J. Jou, “A semi-digital delay-locked loop based on self-biased techniques,” Proc. 10th VLSI Design/CAD Symposium, Aug. 1999, pp. 407-410.

[26] S. J. Jou and C. L. Chen , “FIR filter architecture synthesizer based on CSD code,” Proc. 9th VLSI Design/CAD Symposium, Aug. 1998, pp. 407-410.

[27] S. J. Jou, Ya-Lan Tsao and I-Ying Yang, “All digital phase-locked loop,” Proc. 8th VLSI Design/CAD Symposium, Aug. 1997, pp. 145-148.

[28] Yu-Tao Lin and S. J. Jou, "Simultaneous switching noise analysis and its applications in tapered buffer design,” Proc. 8th VLSI Design/CAD Symposium, Aug. 1997, pp.229-232.

[29] S. J. Jou, T. I. Hsu and C. K. Wang, "Low power digital down converter for wireless communication application, " Proc. 7th VLSI Design/CAD Symposium, Aug. 1996, pp. 135-138.

[30] S. J.  Wen and S. J.  Jou, "Implementation and performance evaluation of recoded multiplier using FPGAs, " Proc. 7th VLSI Design/CAD Symposium, Aug. 1996, pp. 241-244.

[31] S. J.  Jou, T. L.  Chen, "Op amp based voltage converter for LV/LP system," Proc. 6th VLSI Design/CAD Symposium, Aug. 1995, pp. 155-160.

[32] W. H.  Hsieh, S. J. Jou and C. C. Su, "Network hopping technique for simulation tools," Proc. 6th VLSI Design/CAD Symposium, Aug. 1995, pp. 302-305.

[33] S. J. Jou, C. Y. Chen and C. C. Su, "Implementation of high performance multiplier/accumulator", Proc. 5th VLSI Design/CAD Symposium, Aug. 1994, pp. 55-160.

[34] W. H. Hsieh, S. J. Jou and C. C. Su, "PMOTA- A parallel Event-driven MOS timing simulator for distributed-memory multiprocessor," Proc. 5th VLSI Design/CAD Symposium, Aug. 1994, pp.299-303.

[35] Y. M. Lin, C. C. Su, C. K. Wang and S. J. Jou, "MixCAD-A behavioral level mixed-mode system simulator,"  Proc. 5th VLSI Design/CAD Symposium, Aug. 1994, pp.269-274.

[36] S. J. Jou,  K. F. Liu and C. C. Su, "Integrated circuits design optimization using symbolic approach", Proc. 5th VLSI Design/CAD Symposium, Aug. 1994, pp. 310-314.

[37] S. J. Jou, "Symbolic analyzer for general electronic circuits in S- and Z-domain," Proc. 4th VLSI Design/CAD workshop, Aug. 1993, pp.236-239.

[38] S. J. Jou,  W. Z. Shen, C. W. Jen, C. C. Chang, and Y. S. Tao, "Table lookup MOSFET model and the automatic measure system," Proc. EDMS, Taipei, R.O.C., September 3-5. 1986, pp.190-195.

[39] S. J. Jou, W. Z. Shen, C. W. Jen and C. L. Lee, "A MOS logic gate timing model based on dynamic transient behavior," Proc. EDMS, Tainan, R.O.C., Aug.1986, pp.29-34.

 



(C) Academic Books (學術著作)

[1] R. A. Saleh, S. J. Jou and A. R. Newton, Mixed-Mode Simulation and Analog multilevel simulation, Kluwer Academic Publishers, ISBN: 0792394739, 1994

Professional Magazine

[1]  周世傑, 高速運用的平行打散器Engineering Science & Technology Bulletin, NSC, August 2006.

[2]  周世傑, “5 Gbs資料傳輸收發系統-纜線系統之應用,”Engineering Science & Technology Bulletin, NSC, June 2004,  pp.153-158.

[3]  周世傑、林茂青, “數位調變和同步電路技術-傳收系統電路簡介及數位中頻/基頻轉換、時序與載波回復電路設計, “電子月刊第58May. 2000, pp.96-114

[4]周世傑、蘇朝琴,"類比電路電腦輔助工具之概況,"電腦輔助積體電路設計專輯, 電子月刊第七期,Feb. 1996, pp.67-76.



(D) Patents (專利)

1.  周世傑、杜明賢、胡育豪、莊景德、邱奕瑋, STATIC MEMORY AND MEMORY CELL THEREOF , US patent

2.  SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION, US 8,693,237B2, 2014/04/08~2032/09/18

3.莊景德,楊皓義,盧建宇,陳建亨,張琦昕,黃柏蒼,賴淑琳,黃威,周世傑,杜明賢,靜態隨機存取記憶體, (US patent)13/684,784

4. 莊景德、周世傑、林耕慶、王紹丞、林宜緯、蔡銘謙、石維強、連南鈞、李坤地、朱俊愷, 臨界電壓量測裝置, 中華民國發明專利, I425236, 2014/2/1~2032/5/10.

5.  莊景德、周世傑、林耕慶、王紹丞、林宜緯、蔡銘謙、石維強、連南鈞、李坤地、朱俊愷, THRESHOLD VOLTAGE MEASUREMENT DEVICE, US 8,582,378 B1, 2012/08/29~ 2032/08/29

6.周世傑,林志宇,莊景德,杜明賢,邱奕瑋, ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM, USA patent, 2013.

7.Ching-Te Chuang, Hao-I Yang, Jihi-Yu Lin, Shyh-Chyi Yang, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou,  Kun-Ti Lee, Hung-Yu Li, (莊景德、楊皓義、林志宇、楊仕祺、杜明賢、黃威、周世傑、李坤地、李鴻瑜), “Disturb-Free Static Random Access Memory Cell”證書號: 8,259,510(US patent), 2013

8.周世傑,林志憲,鄭元樸,李舒蓉,應用於時脈資料回復電路的多重交替式轉態取樣方法及裝置, 中華民國發明專利, I371922, 2012/9/1 to 2028/5/1.

9.  周世傑,陳筱筠,林志憲,薛木添,用於串列傳輸之傳輸碼, 中華民國發明專利, I-271958, Jan 21 2007 to August 2 2025.

10.S J. Jou and H. H. Wang, Reduced-width low-error multiplier, US patent, 6,957,244 B2, Oct.18 2005 to May 21 2021.

11.周世傑, 陳志寧,王又君,蕭儒遠,林志憲, 串列打散器轉平行打散器之方法,平行打散器及其具互斥或運算之正緣觸發暫存器,中華民國發明專利231655 April, 2005.

12.周世傑,邱瑞德,郭淑華,林挺豪,低雜訊輸出緩衝器, 中華民國發明專利 159431July, 2002.

13.周世傑,王惠萱, 可縮減位元長度式低錯誤乘法器, 中華民國發明專利 155802, April 2002.

14.  S J. Jou, S. H. Kuo, J. T. Chiu and V. Lin, Low-noise output buffer, US patent, 6,265,892 B1, July 2001.

15.  周世傑,陳契霖,劉立國,數位可程式化直流降壓器, 中華民國發明專利第 129523, April 2001.

16.  周世傑,郭淑華,邱瑞德,林挺豪, 可控制上推電阻之輸出緩衝器, 中華民國發明專利第 127683, Feb 2001.

17.  S. J. Jou, C. L. Chen and L. K. Liu,  “Digital Programmable Direct current to Direct Current (DC-DC) Voltage-Down Converter,” US patent, 9,267,879, 2000

18.  薛木添,汪重光,黃光虎,周世傑, ”利用單邊頻譜原理設計之轉換增益可調之電壓控制震盪器”, 中華民國發明專利第 098067,1999.

 

Pending Patent

1. 莊景德、楊皓義、林志宇、楊仕祺、杜明賢、黃威、周世傑、李坤地、李鴻瑜靜態隨機存取記憶體”, 中國(申請號:200910247191.0), 98.12.02

2. 莊景德,石維強,李鴻瑜,林志宇,杜明賢,周世傑,李坤地, 靜態隨機記憶體寫入系統與相關裝置, 中華民國, 申請號:9910893, 申請日 : 2010/03/25

3. 莊景德,石維強,李鴻瑜,林志宇,杜明賢,周世傑,李坤地, 靜態隨機記憶體寫入系統與相關裝置, 中國, 申請號: 201010155533.9, 申請日 : 2010/04/2

4. 莊景德,石維強,李鴻瑜,林志宇,杜明賢,周世傑,李坤地 Replica-Based Transient Negative Bit-Line (NBL) Circuits with Bit-Line Recovery Assist and Write-End to Improve SRAM Write-ability and Cycle-Time/Frequency, USA申請號 : 13/070,977, 申請日 : 2011/03/24

5. 莊景德,楊皓義,夏茂墀,林勇維,盧建宇,杜明賢,黃威,周世傑,陳家政,石維強, "Data-Aware Dynamic Supply Write-Assist Schemes for Cross-Point Addressed SRAM”, USA, 申請案號: 61/361,527, 申請日期:99.07.06.

6. 莊景德,楊皓義,夏茂墀,林勇維,盧建宇,杜明賢,黃威,周世傑,陳家政,石維強,交叉定址結構靜態隨機記憶體之超低功耗操作模式與絕對最低功耗操作模式, 中華民國, 申請號: 100102780, 申請日 : 2011/01/26

7. 莊景德,楊皓義,夏茂墀,林勇維,盧建宇,杜明賢,黃威,周世傑,陳家政,石 維強,交叉定址結構靜態隨機記憶體之超低功耗操作模式與絕對最低功耗操作模式, 中國, 申請號: 201110030858.9, 申請日 : 2011/01/28

8. 莊景德、周世傑、林耕慶、王紹丞、林宜緯、蔡銘謙、石維強、連南鈞、李坤地、朱俊愷, 中華民國專利申請, 申請案號:101116911,    :2012/5/11

9. 桑梓賢/周世傑/張添烜/孫致晴/許碩文/陳柔綾, 人體通道傳輸方法以及系統, 申請日: 20130208日案號: 102105427



(E) Research Reports (研究報告)

[49] 周世傑, 使用60GHz之室內十億級位元傳輸率之無線基頻傳收機-總計畫(2/3), National Science Council, August 2009-July 2010, 97-2220-E-009-026
[48] 周世傑, 使用60GHz之室內十億級位元傳輸率之無線基頻傳收機-子計畫五:室內無線十億級傳輸率之基頻傳收機與低功率設計技術(2/3), National Science Council, August 2009-July 2010, 97-2220-E-009-041
[47] 周世傑, 使用60GHz之室內十億級位元傳輸率之無線基頻傳收機-總計畫(1/3), National Science Council, August 2008-July 2009, 97-2220-E-009-037-
[46] 周世傑, 使用60GHz之室內十億級位元傳輸率之無線基頻傳收機-子計畫五:室內無線十億級傳輸率之基頻傳收機與低功率設計技術(1/3), National Science Council, August 2008-July 2009, 97-2220-E-009-041
[45] 周世傑, 助聽器晶片及系統--子計畫三:助聽器低功率數位電路及SoC整合(2/3), National Science Council, August 2008-July 2009,97-2220-E-009-020
[44] 周世傑, 助聽器晶片及系統--子計畫三:助聽器低功率數位電路及SoC整合(1/3), National Science Council, August 2007-July 2008, 96-2220-E-009-034-
[43] 周世傑,應用於行動無線都會網路基頻傳收機系統晶片之核心技術開發-子計畫三:應用於行動無線都會網路之通道編解碼及低功率核心技術發展(3/3)(95-2220-E-009--)
[42] 周世傑,應用於行動無線都會網路基頻傳收機系統晶片之核心技術開發-總計畫(3/3)(95-2220-E-009--)
[41] 周世傑,應用於行動無線都會網路基頻傳收機系統晶片之核心技術開發-子計畫三:應用於行動無線都會網路之通道編解碼及低功率核心技術發展(2/3)(95-2220-E-009-012-)
[40] 周世傑,應用於行動無線都會網路基頻傳收機系統晶片之核心技術開發-總計畫(2/3)(95-2220-E-009-009-).
[39] 周世傑,應用於行動無線都會網路基頻傳收機系統晶片之核心技術開發-子計畫三:應用於行動無線都會網路之通道編解碼及低功率核心技術發展(1/3)(94-2220-E-009-035-).
[38] 周世傑應用於行動無線都會網路基頻傳收機系統晶片之核心技術開發-總計畫(1/3)(94-2220-E-009-032-).
[37] 周世傑, 數位電視廣播接收器之數位解調與同步設計及其平台與晶片製作(3/3), National Science Council, August 2004-July 2005 NSC 95-2220-E-009-008.
[36] 周世傑, 數位電視廣播接收器之數位解調與同步設計及其平台與晶片製作(2/3), National Science Council, August 2004-July 2005 NSC 94-2220-E-009-031.
[35] 周世傑, 數位電視廣播接收器之數位解調與同步設計及其平台與晶片製作(1/3), National Science Council, August 2004-July 2005 NSC 93-2220-E-009-037.
[34] 周世傑, 奈米級SoC之晶片內通訊傳收機設計, National Science Council, August 2004-July 2005, NSC93-2215-E-009-070.
[33] 周世傑, 奈米級SoC電路之關鍵設計與分析技術-總計畫, National Science Council, August 2004-July 2005, NSC93-2215-E-009-071.
[32] S. J. Jou, 5 Gbps Data Link Transceiver System ; Subject 2: 5 Gbps Data Link Transceiver System for Cable Application (3/3), National Science Council, August 2003-July 2004, NSC92-2215-E-008-003.
[31] S. J. Jou, 5 Gbps Data Link Transceiver System, National Science Council, August 2003-July 2004, NSC92-2215-E-008-001
[30] S. J. Jou, 5 Gbps Data Link Transceiver System ; Subject 2: 5 Gbps Data Link Transceiver System for Cable Application (2/3), National Science Council, August 2002-July 2003, NSC 91-2215-E-008-009.
[29] S. J. Jou, 5 Gbps Data Link Transceiver System (2/3), National Science Council, August 2002-July 2003, NSC91-2215-E-008-007.
[28] S. J. Jou and C. N. Liu, 電戰系統微波控制數位電路縮裝, Chung Shan Institute of Science, Dec. 2002.
[27] S. J. Jou, 5 Gbps Data Link Transceiver System ; Subject 2: 5 Gbps Data Link Transceiver System for Cable Application, National Science Council, August 2001-July 2002, NSC90-2215-E-008-023.
[26] S. J. Jou, 5 Gbps Data Link Transceiver System, National Science Council, August 2001-July 2002, NSC90-2215-E-008-021.
[25] S. J. Jou, XDSL Multimedia and Multi-Service Communication System; Subject 6 :Parameterized DSP Core for XDSL(II), National Science Council, August 2001-July 2002.
[24] W. Z. Chen and S. J. Jou, 2.5 Gbps LD driver IC, 光電所 ITRI, Dec. 2001.
[23] S. J. Jou, Digital Demodulation and Synchronization Design and Chip Implementation for Digital Video Receiver (III), National Science Council, NSC90-2215-E-008-007, August 2001.
[22] W. Z. Chen and S. J. Jou, 1.25 Gbps LD driver IC, 光電所 ITRI, Dec. 2000.
[21] S. J. Jou, Digital Demodulation and Synchronization Design and Chip Implementation for Digital Video Receiver (II), National Science Council, NSC89-2215-E-008-028, August 2000.
[20] S. J. Jou, Analysis of simultaneous switch noise in CMOS integrated circuits and low bouncing output buffer design, National Science Council, NSC88-2215-E-008-024, August 1999.
[19] S. J. Jou, Digital Demodulation and Synchronization Design and Chip Implementation for Digital Video Receiver(I), National Science Council, NSC88-2215-E-008-029, August 1999.
[18] S. J. Jou, S. H. Kuo, J. T. Chiu, SSO Characterization and Estimation of VDD/VSS Pads Requirements for SSOs, Faraday Corp., July 1999.
[17] S. J. Jou, Low-voltage low-power digital circuit design techniques for the IS-95 based CDMA digital IF/Baseband down-converter (III), National Science Council, NSC87-2215-E-008-021, August 1998.
[16] S. J. Jou, Low-voltage low-power VLSI circuit designs for the IS-95 based CDMA acquistion receiver (III), National Science Council, NSC87-2215-E-008-019, August 1998.
[15] S. J. Jou, Low-voltage low-power VLSI circuit designs for the IS-95 based CDMA acquistion receiver (II), National Science Council, NSC86-2221-E-008-023, August 1997.
[14] S. J. Jou, Low-voltage low-power digital circuit design techniques for the IS-95 based CDMA digital IF/Baseband down-converter (II), National Science Council, NSC86-2221-E-008-007, August 1997.
[13] C. K. Wang, S. J. Jou and C. C. Su, Mixed mode low voltage analog and digital VLSI chip designs for telcommunication system (II), Institute of Communication, Ministry of Transportation and communication, Oct. 1996.
[12] S. J. Jou, Low-voltage low-power digital circuit design techniques for the IS-95 based CDMA digital IF/Baseband down-converter, National Science Council, NSC85-2221-E-008-024, August 1996.
[11] C. K. Wang, S. J. Jou and C. C. Su, Mixed mode low voltage analog and digital VLSI chip designs for telcommunication system (I), Institute of Communication, Ministry of Transportation and communication, Oct. 1995..
[10] S. J. Jou, "Parallel and distributed network simulation approach for mixed-mode circuit simulator," NSC 84-2215-E-008-025, August 1995
[9] S. J. Jou, "Macromodeling methodology for continuous and discrete time transfer function," NSC 84-2215-E-008-024, August 1995.
[8] S. J. Jou, "Integrated circuits design optimization using symbolic approach, National Science Council, NSC 83-0404-E-008-008, August 1994.
[7] S. J. Jou , "Analysis and simulation of high-speed multiplier/accumulator", National Science Council, NSC 83-0404-E-008-008, July 1994.
[6] S. J. Jou, "Symbolic analysis tool for mixed signal integrated circuits, National Science Council, NSC 82-04040E008-082, July 1993.
[5] L. M. Tseng, K. T. Chen and S. J. Jou, "High-speed multiplier for HDTV system design",  National Science Council NSC 81-0404 -E-008-106, Aug. 1992.
[4] Y. T. Juang, S. J. Jou and M. K. Tsai, "Circuit analysis and CAD model for RF circuit", Project report,  Chung Shan Institute of Science, Aug. 1992.
[3] S. J. Jou, "A symbolic analysis tool for analog integrated circuits", National Science Council NSC81-0408-E008-07, July 1992.
[2] S. J. Jou, "A MOS circuit and timing fault parallel simulator", National Science Council NSC81-0408-E008-105, Oct. 1992.
[1] S. J. Jou, "The hardware approach to event-driven circuit and timing fault simulator", NSC80-0408-E008-02, Sept. 1991.

Department of Electronics Engineering, National Chiao Tung University
1001 Ta-Hsueh Road, Hsinchu, Taiwan 30010, R.O.C. Tel: +886-3-5712121 ext: 54195